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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. lmr23615-q1 snvsas5 ? march 2018 lmr23615-q1 simple switcher ? 36-v, 1.5-a synchronous step-down converter 1 1 features 1 ? qualified for automotive applications ? aec-q100 qualified with the following results: ? device temperature grade 1: ? 40 c to +125 c ambient operating temperature ? device hbm esd classification level h2 ? device cdm esd classification level c4a ? 4-v to 36-v input range ? 1.5-a continuous output current ? integrated synchronous rectification ? 60-ns minimum switch-on time ? internal compensation for ease of use ? adjustable switching frequency ? pfm mode at light load ? frequency synchronization to external clock ? soft start into a prebiased load ? high duty-cycle operation supported ? output short-circuit protection with hiccup mode ? 12-pin wson wettable flanks package with powerpad ? ? create a custom design using the lmr23615-q1 with the webench ? power designer 2 applications ? automotive infotainment: clusters, head unit, heads-up display ? usb charging ? general off-battery power application space 3 description the lmr23615-q1 simple switcher ? is an easy- to-use 36 v, 1.5 a synchronous step-down regulator. with a wide input range from 4 v to 36 v, the device is suitable for various applications from industrial to automotive for power conditioning from unregulated sources. peak-current-mode control is employed to achieve simple control loop compensation and cycle- by-cycle current limiting. a quiescent current of 75 a makes it suitable for battery-powered systems. an ultra-low 2- a shutdown current can further prolong battery life. internal loop compensation means that the user is free from the tedious task of loop compensation design. this also minimizes the external components. an extended family is available in 2.5-a (lmr23625- q1) and 3-a (lmr23630-q1) load-current options in pin-to-pin compatible packages allowing simple, optimum pcb layout. a precision enable input allows simplification of regulator control and system power sequencing. protection features include cycle-by- cycle current limit, hiccup-mode short-circuit protection, and thermal shutdown due to excessive power dissipation. device information (1) part number package body size (nom) lmr23615-q1 wson (12) 3.00 mm 3.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. space space space simplified schematic efficiency vs load, v in = 12 v boot sw l c boot fb vin v in up to 36 v pgnd c out en/sync c in vcc agnd v out c vcc r fbt r fbb i out (a) efficiency (%) 1e-5 0.0001 0.001 0.01 0.1 1 10 40 50 60 70 80 90 100 lmr2 v out = 5 v v out = 3.3 v tools & software technical documents ordernow productfolder support &community
2 lmr23615-q1 snvsas5 ? march 2018 www.ti.com product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ...................... 4 6.4 thermal information .................................................. 5 6.5 electrical characteristics ........................................... 5 6.6 timing characteristics ............................................... 6 6.7 switching characteristics .......................................... 6 6.8 typical characteristics .............................................. 7 7 detailed description .............................................. 9 7.1 overview ................................................................... 9 7.2 functional block diagram ......................................... 9 7.3 feature description ................................................. 10 7.4 device functional modes ........................................ 16 8 application and implementation ........................ 17 8.1 application information ............................................ 17 8.2 typical applications ................................................ 17 9 power supply recommendations ...................... 23 10 layout ................................................................... 23 10.1 layout guidelines ................................................. 23 10.2 layout example .................................................... 25 11 device and documentation support ................. 26 11.1 device support ...................................................... 26 11.2 receiving notification of documentation updates 26 11.3 community resources .......................................... 26 11.4 trademarks ........................................................... 26 11.5 electrostatic discharge caution ............................ 26 11.6 glossary ................................................................ 26 12 mechanical, packaging, and orderable information ........................................................... 27 4 revision history date revision notes march 2018 * initial release
3 lmr23615-q1 www.ti.com snvsas5 ? march 2018 product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) a = analog, p = power, g = ground. 5 pin configuration and functions drr package 12-pin wson with rt top view pin functions pin i/o (1) description no. name 1, 2 sw p switching output of the regulator. internally connected to both power mosfets. connect to power inductor. 3 boot p boot-strap capacitor connection for high-side driver. connect a high-quality, 100-nf capacitor from boot to sw. 4 vcc p internal bias supply output for bypassing. connect a 2.2- f, 16-v or higher capacitance bypass capacitor from this pin to agnd. do not connect external loading to this pin. never short this pin to ground during operation. 5 fb a feedback input to regulator, connect the feedback resistor divider tap to this pin. 6 rt a connect a resistor rt from this pin to agnd to program switching frequency. leave floating for 400-khz default switching frequency. 7 agnd g analog ground pin. ground reference for internal references and logic. connect to system ground. 8 en/sync a enable input to regulator. high = on, low = off. can be connected to vin. do not float. adjust the input undervoltage lockout with two resistors. the internal oscillator can be synchronized to an external clock by coupling a positive pulse into this pin through a small coupling capacitor. see en/sync for detail. 9, 10 vin p input supply voltage. 11 nc n/a not for use. leave this pin floating. 12 pgnd g power ground pin, connected internally to the low side power fet. connect to system ground, pad, agnd, ground pins of c in and c out . path to c in must be as short as possible. 13 pad g low impedance connection to agnd. connect to pgnd on pcb. major heat dissipation path of the die. must be used for heat sinking to ground plane on pcb. sw sw boot vcc fb rt pgnd nc vin vin en/ sync agnd 12 3 4 5 6 12 11 10 98 7 pad 13
4 lmr23615-q1 snvsas5 ? march 2018 www.ti.com product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) in shutdown mode, the vcc to agnd maximum value is 5.25 v. 6 specifications 6.1 absolute maximum ratings over the recommended operating junction temperature range of ? 40 c to +125 c (unless otherwise noted) (1) parameter min max unit input voltages vin to pgnd ? 0.3 42 v en/sync to agnd ? 5.5 42 fb to agnd ? 0.3 4.5 rt to agnd ? 0.3 4.5 agnd to pgnd ? 0.3 0.3 output voltages sw to pgnd ? 1 v in + 0.3 v sw to pgnd less than 10-ns transients ? 5 42 boot to sw ? 0.3 5.5 vcc to agnd ? 0.3 4.5 (2) junction temperature, t j ? 40 150 c storage temperature, t stg ? 65 150 c (1) aec q100-002 indicates that hbm stressing shall be in accordance with the ansi/esda/jedec js-001 specification. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm) (1) 2500 v charged-device model (cdm) 1000 (1) recommended operating ratings indicate conditions for which the device is intended to be functional, but do not ensured specific performance limits. for specified specifications, see electrical characteristics . 6.3 recommended operating conditions over the recommended operating junction temperature range of ? 40 c to 125 c (unless otherwise noted) (1) min max unit input voltage vin 4 36 v en/sync ? 5 36 fb ? 0.3 1.2 output voltage, v out 1 28 v output current, i out 0 1.5 a operating junction temperature, t j ? 40 125 c
5 lmr23615-q1 www.ti.com snvsas5 ? march 2018 product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. (2) determine power rating at a specific ambient temperature (t a ) with a maximum junction temperature (t j ) of 125 c, which is illustrated in recommended operating conditions section. 6.4 thermal information thermal metric (1) (2) lmr23615-q1 unit ddr (wson) 12 pins r ja junction-to-ambient thermal resistance 41.5 c/w r jc(top) junction-to-case (top) thermal resistance 0.3 c/w r jb junction-to-board thermal resistance 16.5 c/w jt junction-to-top characterization parameter 39.1 c/w jb junction-to-board characterization parameter 3.4 c/w r jc(bot) junction-to-case (bottom) thermal resistance 16.3 c/w 6.5 electrical characteristics limits apply over the recommended operating junction temperature (t j ) range of ? 40 c to +125 c, unless otherwise stated. minimum and maximum limits are specified through test, design or statistical correlation. typical values represent the most likely parametric norm at t j = 25 c, and are provided for reference purposes only. parameter test conditions min typ max unit power supply (vin pin) v in operation input voltage 4 36 v vin_uvlo undervoltage lockout thresholds rising threshold 3.3 3.7 3.9 v falling threshold 2.9 3.3 3.5 i shdn shutdown supply current v en = 0 v, v in = 12 v, t j = ? 40 c to 125 c 2 4 a i q operating quiescent current (non- switching) v in =12 v, v fb = 1.2 v, t j = ? 40 c to 125 c 75 a enable (en/sync pin) v en_h enable rising threshold voltage 1.4 1.55 1.7 v v en_hys enable hysteresis voltage 0.4 v v wake wake-up threshold 0.4 v i en input leakage current at en pin v in = 4 v to 36 v, v en = 2 v 10 100 na v in = 4 v to 36 v, v en = 36 v 1 a voltage reference (fb pin) v ref reference voltage v in = 4 v to 36 v, t j = 25 c 0.985 1 1.015 v v in = 4 v to 36 v, t j = ? 40 c to 125 c 0.98 1 1.02 i lkg_fb input leakage current at fb pin v fb = 1 v 10 na internal ldo (vcc pin) v cc internal ldo output voltage 4.1 v vcc_uvlo vcc undervoltage lockout thresholds rising threshold 2.8 3.2 3.6 v falling threshold 2.4 2.8 3.2 current limit i hs_limit peak inductor current limit 2.9 3.9 4.9 a i ls_limit valley inductor current limit 1.9 2.5 3.2 a i l_zc zero cross current limit ? 0.04 a integrated mosfets r ds_on_hs high-side mosfet on-resistance v in = 12 v, i out = 1 a 160 m ? r ds_on_ls low-side mosfet on-resistance v in = 12 v, i out = 1 a 95 m ? thermal shutdown t shdn thermal shutdown threshold 162 170 178 c t hys hysteresis 15 c
6 lmr23615-q1 snvsas5 ? march 2018 www.ti.com product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) specified by design. 6.6 timing characteristics over the recommended operating junction temperature range of ? 40 c to +125 c (unless otherwise noted) min nom max unit hiccup mode n oc (1) number of cycles that ls current limit is tripped to enter hiccup mode 64 cycles t oc hiccup retry delay time 10 ms soft start t ss internal soft-start time. the time of internal reference to increase from 0 v to 1 v 6 ms (1) specified by design. 6.7 switching characteristics over the recommended operating junction temperature range of ? 40 c to +125 c (unless otherwise noted) parameter test condition min typ max unit sw (sw pin) t on_min minimum turnon time 60 90 ns t off_min (1) minimum turnoff time 100 ns sync (en/sync pin) f sw oscillator default frequency rt pin open circuit 340 400 460 khz f adj minimum adjustable frequency rt = 198 k with 1% accuracy 150 200 250 khz maximum adjustable frequency rt = 17.8 k with 1% accuracy 1750 2150 2425 f sync sync frequency range 200 2200 khz v sync amplitude of sync clock ac signal (measured at sync pin) 2.8 5.5 v t sync_min minimum sync clock on and off time 100 ns
7 lmr23615-q1 www.ti.com snvsas5 ? march 2018 product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.8 typical characteristics unless otherwise specified the following conditions apply: v in = 12 v, f sw = 1600 khz, l = 4.7 h, c out = 47 f, t a = 25 c. f sw = 1000 khz v out = 5 v figure 1. efficiency vs load current f sw = 1000 khz v out = 3.3 v figure 2. efficiency vs load current f sw = 2200 khz v out = 5 v figure 3. efficiency vs load current f sw = 2200 khz v out = 3.3 v figure 4. efficiency vs load current f sw = 1000 khz v out = 5 v figure 5. load regulation f sw = 1000 khz v out = 5 v figure 6. line regulation i out (a) efficiency (%) 1e-5 0.0001 0.001 0.01 0.1 1 10 0 10 20 30 40 50 60 70 80 90 100 lmr2 v in = 12 v v in = 24 v v in = 36 v i out (a) efficiency (%) 1e-5 0.0001 0.001 0.01 0.1 1 10 0 10 20 30 40 50 60 70 80 90 100 lmr2 v in = 8 v v in = 12 v v in = 24 v i out (a) efficiency (%) 1e-5 0.0001 0.001 0.01 0.1 1 10 0 10 20 30 40 50 60 70 80 90 100 lmr2 v in = 8 v v in = 12 v v in = 24 v i out (a) efficiency (%) 1e-5 0.0001 0.001 0.01 0.1 1 10 0 10 20 30 40 50 60 70 80 90 100 lmr2 v in = 8 v v in = 12 v v in = 20 v v in (v) v out (v) 5 10 15 20 25 30 35 40 5.01 5.02 5.03 5.04 5.05 5.06 5.07 5.08 5.09 5.1 lmr2 i out = 1.5 a i out = 0.2 a i out = 0 a i out (a) v out (v) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 5.01 5.02 5.03 5.04 5.05 5.06 5.07 5.08 5.09 5.1 5.11 5.12 lmr2 v in = 12 v v in = 24 v v in = 36 v
8 lmr23615-q1 snvsas5 ? march 2018 www.ti.com product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) unless otherwise specified the following conditions apply: v in = 12 v, f sw = 1600 khz, l = 4.7 h, c out = 47 f, t a = 25 c. f sw = 1000 khz v out = 5 v figure 7. dropout curve f sw = 2200 khz v out = 5 v figure 8. dropout curve v in = 12 v v fb = 1.1 v figure 9. i q vs junction temperature figure 10. vin uvlo rising threshold vs junction temperature figure 11. vin uvlo hysteresis vs junction temperature v in = 12 v figure 12. hs and ls current limit vs junction temperature temperature ( q c) current limit (a) -50 0 50 100 150 2 2.5 3 3.5 4 4.5 lmr2 ls limit hs limit temperature (c) v in uvlo hysteresis (v) -50 0 50 100 150 0.41 0.415 0.42 0.425 d010 v in (v) v out (v) 4 4.5 5 5.5 6 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 lmr2 i out = 0 a i out = 0.2 a i out = 0.8 a i out = 1.5 a v in (v) v out (v) 4 4.5 5 5.5 6 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 lmr2 i out = 0 a i out = 0.2 a i out = 0.8 a i out = 1.5 a temperature (c) v in uvlo rising threshold (v) -50 0 50 100 150 3.61 3.62 3.63 3.64 3.65 3.66 3.67 d009 temperature (c) iq (a) -50 0 50 100 150 60 65 70 75 80 d008
9 lmr23615-q1 www.ti.com snvsas5 ? march 2018 product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 detailed description 7.1 overview the lmr23615-q1 simple switcher regulator is an easy-to-use synchronous step-down dc/dc converter operating from 4-v to 36-v supply voltage. the device is capable of delivering up to 1.5-a dc load current with good thermal performance in a small solution size. an extended family is available in multiple current options from 1.5 a to 3 a in pin-to-pin compatible packages. the lmr23615-q1 employs fixed-frequency peak-current-mode control. the device enters pfm mode at light load to achieve high efficiency. the device is internally compensated, which reduces design time and requires few external components. the switching frequency is adjustable from 200 khz to 2.2 mhz, leave rt pin open for 400-khz default switching frequency. the lmr23615-q1 is capable of synchronization to an external clock within the range of 200 khz to 2.2 mhz. additional features such as precision enable and internal soft start provide a flexible and easy-to-use solution for a wide range of applications. protection features include thermal shutdown, vin and vcc undervoltage lockout (uvlo), cycle-by-cycle current limit, and hiccup-mode short-circuit protection. the family requires very few external components and has a pinout designed for simple, optimum pcb layout. 7.2 functional block diagram ea ref en/sync sw cboot vcc internal ss ov/uv detector oscillator precision enable ldo pfm detector slope comp pwm control logic uvlo tsd freq foldback zero cross hiccup detector vin rc cc pgnd fb ls i sense hs i sense fb vcc enable sync detector sync signal sync signal agnd rt copyright ? 2017, texas instruments incorporated
10 lmr23615-q1 snvsas5 ? march 2018 www.ti.com product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3 feature description 7.3.1 fixed-frequency peak-current-mode control the following operating description of the lmr23615-q1 refers to the functional block diagram and to the waveforms in figure 13 . the lmr23615-q1 is a step-down synchronous buck regulator with integrated high-side (hs) and low-side (ls) switches (synchronous rectifier). the lmr23615-q1 supplies a regulated output voltage by turning on the hs and ls nmos switches with controlled duty cycle. during high-side switch on-time, the sw pin voltage swings up to approximately v in , and the inductor current i l increase with linear slope (v in ? v out ) / l. when the hs switch is turned off by the control logic, the ls switch is turned on after an anti-shoot-through dead time. inductor current discharges through the ls switch with a slope of ? v out / l. the control parameter of a buck converter is defined as duty cycle d = t on / t sw , where t on is the high-side switch on-time and t sw is the switching period. the regulator control loop maintains a constant output voltage by adjusting the duty cycle d. in an ideal buck converter, where losses are ignored, d is proportional to the output voltage and inversely proportional to the input voltage: d = v out / v in . figure 13. sw node and inductor current waveforms in continuous conduction mode (ccm) the lmr23615-q1 employs fixed-frequency peak-current-mode control. a voltage feedback loop is used for accurate dc voltage regulation by adjusting the peak current command based on voltage offset. the peak inductor current is sensed from the high-side switch and compared to the peak current threshold to control the on-time of the high-side switch. the voltage feedback loop is internally compensated, which allows for fewer external components, makes it easy to design, and provides stable operation with almost any combination of output capacitors. the regulator operates with fixed switching frequency at normal load condition. at light load condition, the lmr23615-q1 operates in pfm mode to maintain high efficiency. 7.3.2 adjustable frequency the switching frequency can be programmed by the impedance r t from the rt pin to ground. the frequency is inversely proportional to the r t resistance. the rt pin can be left floating and the lmr23615 will operate at 400 khz default switching frequency. the rt pin is not designed to be shorted to ground. for a desired frequency, typical r t resistance can be found by equation 1 . table 1 gives typical r t values for a given f sw . r t (k ) = 40200 / f sw (khz) ? 0.6 (1) v sw v in d = t on / t sw t on t off t sw t -v d 0 sw voltage i l i out t 0 inductor current i lpk ' i l
11 lmr23615-q1 www.ti.com snvsas5 ? march 2018 product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) figure 14. rt vs frequency curve table 1. typical frequency setting rt resistance f sw (khz) r t (k ? ) 200 200 350 115 500 78.7 750 53.6 1000 39.2 1500 26.1 2000 19.6 2200 17.8 7.3.3 adjustable output voltage a precision 1-v reference voltage is used to maintain a tightly regulated output voltage over the entire operating temperature range. the output voltage is set by a resistor divider from output voltage to the fb pin. ti recommends using 1% tolerance resistors with a low temperature coefficient for the fb divider. select the low- side resistor r fbb for the desired divider current and use equation 2 to calculate high-side r fbt . r fbt in the range from 10 k ? to 100 k ? is recommended for most applications. a lower r fbt value can be used if static loading is desired to reduce v out offset in pfm operation. lower r fbt reduces efficiency at very light load. less static current goes through a larger r fbt and might be more desirable when light load efficiency is critical. but r fbt larger than 1 m is not recommended because it makes the feedback path more susceptible to noise. larger r fbt value requires more carefully designed feedback path on the pcb. the tolerance and temperature variation of the resistor dividers affect the output voltage regulation. figure 15. output voltage setting (2) out ref fbt fbb ref v v r r v u 0 50 100 150 200 250 0 500 1000 1500 2000 2500 rt resistance (k ? ) switching frequency (khz) c008 v out fb r fbt r fbb
12 lmr23615-q1 snvsas5 ? march 2018 www.ti.com product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.4 en/sync the voltage on the en/sync pin controls the on or off operation of lmr23615-q1. a voltage less than 1 v (typical) shuts down the device while a voltage higher than 1.6 v (typical) is required to start the regulator. the en pin is an input and cannot be left open or floating. the simplest way to enable the operation of the lmr23615-q1 is to connect the en to v in . this allows self-start-up of the lmr23615-q1 when v in is within the operation range. many applications benefit from the employment of an enable divider r ent and r enb ( figure 16 ) to establish a precision system uvlo level for the converter. system uvlo can be used for supplies operating from utility power as well as battery power. it can be used for sequencing, ensuring reliable operation, or supply protection, such as a battery discharge level. an external logic signal can also be used to drive en input for system sequencing and protection. figure 16. system uvlo by enable divider the en/sync pin also can be used to synchronize the internal oscillator to an external clock. the internal oscillator can be synchronized by ac coupling a positive edge into the en/sync pin. the ac coupled peak-to- peak voltage at the en/sync pin must exceed the sync amplitude threshold of 2.8 v (typical) to trip the internal synchronization pulse detector, and the minimum sync clock on- and off-times must be longer than 100 ns (typical). a 3.3-v or a higher amplitude pulse signal coupled through a 1-nf capacitor c sync is a good starting point. keeping r ent // r enb (r ent parallel with r enb ) in the 100-k ? range is a good choice. r ent is required for this synchronization circuit, but r enb can be left unmounted if system uvlo is not needed. lmr23615-q1 switching action can be synchronized to an external clock from 200 khz to 2.2 mhz. figure 18 and figure 19 show the device synchronized to an external system clock. figure 17. synchronize to external clock r ent en/sync vin r enb r ent clock source en/sync c sync vin r enb
13 lmr23615-q1 www.ti.com snvsas5 ? march 2018 product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 18. synchronizing in pwm mode figure 19. synchronizing in pfm mode 7.3.5 vcc, uvlo the lmr23615-q1 integrates an internal ldo to generate v cc for control circuitry and mosfet drivers. the nominal voltage for v cc is 4.1 v. the vcc pin is the output of an ldo and must be properly bypassed. place high-quality ceramic capacitor with a value of 2.2 f to 10 f, 16 v or higher rated voltage as close as possible to vcc and grounded to the exposed pad and ground pins. the vcc output pin must not be loaded or shorted to ground during operation. shorting vcc to ground during operation may cause damage to the lmr23615-q1. vcc uvlo prevents the lmr23615-q1 from operating until the v cc voltage exceeds 3.3 v (typical). the vcc uvlo threshold has 400 mv (typical) of hysteresis to prevent undesired shutdown due to temporary v in drops. 7.3.6 minimum on-time, minimum off-time and frequency foldback at dropout conditions minimum on-time, t on_min , is the smallest duration of time that the hs switch can be on. t on_min is typically 60 ns in the lmr23615-q1. minimum off-time, t off_min , is the smallest duration that the hs switch can be off. t off_min is typically 100 ns in the lmr23615-q1. in ccm operation, t on_min and t off_min limit the voltage conversion range given a selected switching frequency. the minimum duty cycle allowed is: d min = t on_min f sw (3) and the maximum duty cycle allowed is: d max = 1 ? t off_min f sw (4) given fixed t on_min and t off_min , the higher the switching frequency the narrower the range of the allowed duty cycle. in the lmr23615-q1, a frequency foldback scheme is employed to extend the maximum duty cycle when t off_min is reached. the switching frequency decreases once longer duty cycle is needed under low v in conditions. wide range of frequency foldback allows the lmr23615-q1 output voltage stay in regulation with a much lower supply voltage v in . this leads to a lower effective drop-out voltage. given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution size and efficiency. the maximum operation supply voltage can be found by: (5) at lower supply voltage, the switching frequency decreases once t off_min is tripped. the minimum v in without frequency foldback can be approximated by: (6) taking considerations of power losses in the system with heavy load operation, v in_max is higher than the result calculated in equation 5 . with frequency foldback, v in_min is lowered by decreased f sw . out in _ min sw off _ min v v 1 f t u out in _ max sw on _ min v v f t u
14 lmr23615-q1 snvsas5 ? march 2018 www.ti.com product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 20. frequency foldback at dropout (v out = 5 v, f sw = 2100 khz) 7.3.7 internal compensation and c ff the lmr23615-q1 is internally compensated as shown in functional block diagram . the internal compensation is designed such that the loop response is stable over the entire operating frequency and output voltage range. depending on the output voltage, the compensation loop phase margin can be low with all ceramic capacitors. an external feed-forward capacitor c ff is recommended to be placed in parallel with the top resistor divider r fbt for optimum transient performance. figure 21. feedforward capacitor for loop compensation the feed-forward capacitor c ff in parallel with r fbt places an additional zero before the cross over frequency of the control loop to boost phase margin. the zero frequency can be found by (7) an additional pole is also introduced with c ff at the frequency of (8) the zero f z_cff adds phase boost at the crossover frequency and improves transient response. the pole f p-cff helps maintaining proper gain margin at frequency beyond the crossover. table 2 lists the combination of c out , c ff and r fbt for typical applications, designs with similar c out but r fbt other than recommended value, please adjust c ff such that (c ff r fbt ) is unchanged and adjust r fbb such that (r fbt / r fbb ) is unchanged. p _ cff ff fbt fbb 1 f 2 c r //r s u u z _ cff ff fbt 1 f 2 c r s u u r fbt fb v out r fbb c ff input voltage (v) switching frequency (khz) 5 5.5 6 6.5 7 7.5 8 0 500 1000 1500 2000 2500 lmr2 0.5 a 1.0 a 1.5 a
15 lmr23615-q1 www.ti.com snvsas5 ? march 2018 product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated designs with different combinations of output capacitors need different c ff . different types of capacitors have different equivalent series resistance (esr). ceramic capacitors have the smallest esr and need the most c ff . electrolytic capacitors have much larger esr, and the esr zero frequency would be low enough to boost the phase up around the crossover frequency. designs using mostly electrolytic capacitors at the output may not need any c ff . (9) the c ff creates a time constant with r fbt that couples in the attenuate output voltage ripple to the fb node. if the c ff value is too large, it can couple too much ripple to the fb and affect v out regulation. therefore, calculate c ff base on output capacitors used in the system. at cold temperatures, the value of c ff might change based on the tolerance of the chosen component. this may reduce its impedance and ease noise coupling on the fb node. to avoid this, more capacitance can be added to the output or the value of c ff can be reduced. 7.3.8 bootstrap voltage (boot) the lmr23615-q1 provides an integrated bootstrap voltage regulator. a small capacitor between the boot and sw pins provides the gate-drive voltage for the high-side mosfet. the boot capacitor is refreshed when the high-side mosfet is off and the low-side switch conducts. the recommended value of the boot capacitor is 0.1 f. for stable performance, ti recommends a ceramic capacitor with an x7r or x5r grade dielectric with a voltage rating of 16 v or higher over temperature and voltage. 7.3.9 overcurrent and short-circuit protection the lmr23615-q1 is protected from overcurrent conditions by cycle-by-cycle current limit on both the peak and valley of the inductor current. hiccup mode is activated if a fault condition persists to prevent overheating. high-side mosfet over-current protection is implemented by the nature of the peak-current-mode control. the hs switch current is sensed when the hs is turned on after a set blanking time. the hs switch current is compared to the output of the error amplifier (ea) minus slope compensation every switching cycle. see functional block diagram for more details. the peak current of hs switch is limited by a clamped maximum peak current threshold i hs_limit , which is constant. thus, the peak current limit of the high-side switch is not affected by the slope compensation and remains constant over the full duty cycle range. the current going through ls mosfet is also sensed and monitored. when the ls switch turns on, the inductor current begins to ramp down. the ls switch is not turned off at the end of a switching cycle if its current is above the ls current limit i ls_limit . the ls switch is kept on so that inductor current keeps ramping down, until the inductor current ramps below the ls current limit i ls_limit . the ls switch is then turned off, and the hs switch is turned on after a dead time. this is somewhat different than the more typical peak-current limit and results in equation 10 for the maximum load current. (10) if the current of the ls switch is higher than the ls current limit for 64 consecutive cycles, hiccup current- protection mode is activated. in hiccup mode the regulator is shut down and kept off for 5 ms typically before the lmr23615-q1 tries to start again. if overcurrent or short-circuit fault condition still exists, hiccup repeats until the fault condition is removed. hiccup mode reduces power dissipation under severe overcurrent conditions, prevents overheating and potential damage to the device. 7.3.10 thermal shutdown the lmr23615-q1 provides an internal thermal shutdown to protect the device when the junction temperature exceeds 170 c (typical). the device is turned off when thermal shutdown activates. once the die temperature falls below 155 c (typical), the device reinitiates the power up sequence controlled by the internal soft-start circuitry. z _esr out 1 f 2 c esr s u u in out out out _ max ls _ limit sw in v v v i i 2 f l v u u u
16 lmr23615-q1 snvsas5 ? march 2018 www.ti.com product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.4 device functional modes 7.4.1 shutdown mode the en pin provides electrical on and off control for the lmr23615-q1. when v en is below 1 v (typical), the device is in shutdown mode. the lmr23615-q1 also employs vin and vcc uvlo protection. if v in or v cc voltage is below their respective uvlo level, the regulator is turned off. 7.4.2 active mode the lmr23615-q1 is in active mode when v en is above the precision enable threshold, v in and v cc are above their respective uvlo level. the simplest way to enable the lmr23615-q1 is to connect the en/sync pin to vin pin. this allows self startup when the input voltage is in the operating range: 4 v to 36 v. see vcc, uvlo and en/sync for details on setting these operating levels. in active mode, depending on the load current, the lmr236215-q1 is in one of three modes: 1. continuous conduction mode (ccm) with fixed switching frequency when load current is above half of the peak-to-peak inductor current ripple. 2. discontinuous conduction mode (dcm) with fixed switching frequency when load current is lower than half of the peak-to-peak inductor current ripple in ccm operation (only for pfm option). 3. pulse frequency modulation mode (pfm) when switching frequency is decreased at very light load (only for pfm option). 7.4.3 ccm mode ccm operation is employed in the lmr23615-q1 when the load current is higher than half of the peak-to-peak inductor current. in ccm operation, the frequency of operation is fixed, output voltage ripple is at a minimum in this mode, and the maximum output current of 1.5 a can be supplied by the lmr23615-q1. 7.4.4 light load operation when the load current is lower than half of the peak-to-peak inductor current in ccm, the lmr23615-q1 operates in dcm, also known as diode emulation mode (dem). in dcm, the ls switch is turned off when the inductor current drops to i l_zc ( ? 40 ma typical). both switching losses and conduction losses are reduced in dcm, compared to forced pwm operation at light load. at even lighter current loads, pfm is activated to maintain high efficiency operation. when either the minimum hs switch on-time (t on_min ) or the minimum peak inductor current i peak_min (300 ma typical) is reached, the switching frequency decreases to maintain regulation. in pfm, switching frequency is decreased by the control loop when load current reduces to maintain output voltage regulation. switching loss is further reduced in pfm operation due to less frequent switching actions. the external clock synchronizing is not valid when lmr23615- q1 enters into pfm mode.
17 lmr23615-q1 www.ti.com snvsas5 ? march 2018 product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the lmr23615-q1 is a step-down dc-to-dc regulator. it is typically used to convert a higher dc voltage to a lower dc voltage with a maximum output current of 1.5 a. the following design procedure can be used to select components for the lmr23615-q1. alternately, the webench software may be used to generate complete designs. when generating a design, the webench software utilizes iterative design procedure and accesses comprehensive databases of components. see custom design with webench ? tools and ti.com for more details. 8.2 typical applications the lmr23615-q1 only requires a few external components to convert from a wide voltage range supply to a fixed output voltage. figure 22 shows a basic schematic. figure 22. application circuit the external components have to fulfill the needs of the application, but also the stability criteria of the device's control loop. table 2 can be used to simplify the output filter component selection. boot sw 4.7 h 0.1 f fb vin v in 12 v pgnd 33 f en/ sync 10 f vcc agnd v out 5 v/1.5 a 2.2 f 88.7 n? 22.1 n? pad 22 pf c boot c out c in c vcc r fbt r fbb c ff l r t rt 24.3 n? copyright ? 2017, texas instruments incorporated
18 lmr23615-q1 snvsas5 ? march 2018 www.ti.com product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated typical applications (continued) (1) inductance value is calculated based on v in = 36 v. (2) all the c out values are after derating. add more when using ceramic capacitors. (3) high esr c out will give enough phase boost and c ff not needed. (4) r fbt = 0 for v out = 1 v. r fbb = 22.1 k for all other v out setting. (5) for designs with r fbt other than recommended value, adjust c ff such that (c ff r fbt ) is unchanged and adjust r fbb such that (r fbt / r fbb ) is unchanged. table 2. l, c out , and c ff typical values f sw (khz) v out (v) l ( h) (1) c out ( f) (2) c ff (pf) (3) r fbt (k ) (4) (5) 200 3.3 22 200 220 51 5 33 150 120 88.7 12 56 68 see note (3) 243 24 56 33 see note (3) 510 400 3.3 10 120 100 51 5 15 90 68 88.7 12 33 47 see note (3) 243 24 33 22 see note (3) 510 1000 3.3 4.7 68 47 51 5 5.6 47 22 88.7 12 10 33 see note (3) 243 2200 3.3 2.2 33 22 51 5 3.3 22 15 88.7 8.2.1 design requirements detailed design procedure is described based on a design example. for this design example, use the parameters listed in table 3 as the input parameters. table 3. design example parameters design parameter example value input voltage, v in 12 v typical, range from 8 v to 28 v output voltage, v out 5 v maximum output current i o_max 1.5 a transient response 0.2 a to 2.5 a 5% output voltage ripple 50 mv input voltage ripple 400 mv switching frequency f sw 1600 khz
19 lmr23615-q1 www.ti.com snvsas5 ? march 2018 product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2.2 detailed design procedure 8.2.2.1 custom design with webench ? tools click here to create a custom design using the lmr23615-q1 device with the webench ? power designer. 1. start by entering the input voltage (v in ), output voltage (v out ), and output current (i out ) requirements. 2. optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. compare the generated design with other possible solutions from texas instruments. the webench power designer provides a customized schematic along with a list of materials with real-time pricing and component availability. in most cases, these actions are available: ? run electrical simulations to see important waveforms and circuit performance ? run thermal simulations to understand board thermal performance ? export customized schematic and layout into popular cad formats ? print pdf reports for the design, and share the design with colleagues get more information about webench tools at www.ti.com/webench . 8.2.2.2 output voltage setpoint the output voltage of lmr23615-q1 is externally adjustable using a resistor divider network. the divider network is comprised of top feedback resistor r fbt and bottom feedback resistor r fbb . equation 11 is used to determine the output voltage: (11) choose the value of r fbb to be 22.1 k ? . with the desired output voltage set to 5 v and the v ref = 1 v, the r fbb value can then be calculated using equation 11 . the formula yields to a value 88.7 k ? . 8.2.2.3 switching frequency the switching frequency can be adjusted by rt resistance from rt pin to ground. use equation 1 to calculate the required value of r t . the device can also be synchronized to an external clock for a desired frequency, please refer to en/sync for more details. for 1600 khz frequency, the calculated r t is 24.5 k , and standard value 24.3 k is selected to set the frequency approximate to 1600 khz. 8.2.2.4 inductor selection the most critical parameters for the inductor are the inductance, saturation current and the rated current. the inductance is based on the desired peak-to-peak ripple current i l . since the ripple current increases with the input voltage, the maximum input voltage is always used to calculate the minimum inductance l min . use equation 13 to calculate the minimum value of the output inductor. k ind is a coefficient that represents the amount of inductor ripple current relative to the maximum output current of the device. a reasonable value of k ind should be 20% to 40%. during an instantaneous short-current or overcurrent operation event, the rms and peak inductor current can be high. the inductor current rating must be higher than the current limit of the device. (12) (13) out in _ max out l in _ max sw v v v i v l f u ' u u out ref fbt fbb ref v v r r v u in _ max out out min out ind in _ max sw v v v l i k v f u u u
20 lmr23615-q1 snvsas5 ? march 2018 www.ti.com product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated in general, it is preferable to choose lower inductance in switching power supplies, because it usually corresponds to faster transient response, smaller dcr, and reduced size for more compact designs. but too low of an inductance can generate too large of an inductor current ripple such that overcurrent protection at the full load could be falsely triggered. it also generates more conduction loss and inductor core loss. larger inductor current ripple also implies larger output voltage ripple with same output capacitors. with peak current mode control, it is not recommended to have too small of an inductor current ripple. a larger peak current ripple improves the comparator signal to noise ratio. for this design example, choose k ind = 0.4, the minimum inductor value is calculated to be 1.9 h. choose the nearest standard 2.2- h ferrite inductor with a capability of 3.5-a rms current, and 6-a saturation current. 8.2.2.5 output capacitor selection choose the output capacitor(s), c out , with care because output capacitance directly affects the steady-state output-voltage ripple, loop stability, and the voltage over/undershoot during load current transients. the output ripple is essentially composed of two parts. one is caused by the inductor current ripple going through the esr of the output capacitors: (14) the other is caused by the inductor current ripple charging and discharging the output capacitors: (15) the two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the sum of two peaks. output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation with presence of large current steps and fast slew rate. when a fast large-load increase uccurs, output capacitors provide the required charge before the inductor current can slew up to the appropriate level. the regulator control loop usually needs six or more clock cycles to respond to the output voltage droop. the output capacitance must be large enough to supply the current difference for six clock cycles to maintain the output voltage within the specified range. equation 16 shows the minimum output capacitance needed for specified output undershoot. when a sudden large load decrease happens, the output capacitors absorb energy stored in the inductor resulting in an output voltage overshoot. equation 17 calculates the minimum capacitance required to keep the voltage overshoot within a specified range. (16) where ? k ind = ripple ratio of the inductor ripple current ( i l / i out ) ? i ol = low level output current during load transient ? i oh = high level output current during load transient ? v us = target output voltage undershoot ? v os = target output voltage overshoot (17) for this design example, the target output ripple is 50 mv. presuppose v out_esr = v out_c = 50 mv, and chose k ind = 0.4. equation 14 yields esr no larger than 83.3 m ? and equation 15 yields c out no smaller than 0.9 f. for the target over/undershoot range of this design, v us = v os = 5% v out = 250 mv. the c out can be calculated to be no smaller than 14 f and 4.1 f by equation 16 and equation 17 , respectively. consider of derating, one 33- f, 16 v ceramic capacitor with 5 m ? esr is used. ind out l out _ c sw out sw out k i i v 8 f c 8 f c u ' ' u u u u out_esr l ind out v i esr k i esr ' ' u u u 2 2 oh ol out 2 2 out os out i i c (v v ) v ! oh ol out sw us 4 i i c f v u ! u
21 lmr23615-q1 www.ti.com snvsas5 ? march 2018 product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2.2.6 feed-forward capacitor the lmr23615-q1 is internally compensated. depending on the v out and frequency f sw , if the output capacitor c out is dominated by low esr (ceramic types) capacitors, it could result in low phase margin. to improve the phase boost an external feed-forward capacitor c ff can be added in parallel with r fbt . choose c ff so that phase margin is boosted at the crossover frequency without c ff . a simple estimation for the crossover frequency (f x ) without c ff is shown in equation 18 , assuming c out has very small esr, and c out value is after derating. (18) equation 19 for c ff was tested: (19) for designs with higher esr, c ff is not needed when c out has very high esr; reduce c ff calculated from equation 19 with medium esr. table 2 can be used as a quick starting point. for the application in this design example, a 18-pf, 50-v cog capacitor is selected. 8.2.2.7 input capacitor selection the lmr23615-q1 device requires high-frequency input decoupling capacitor(s) and a bulk input capacitor, depending on the application. the typical recommended value for the high frequency decoupling capacitor is 4.7 f to 10 f. ti recommends a high-quality ceramic capacitor type x5r or x7r with sufficiency voltage rating is recommended. to compensate the derating of ceramic capacitors, a voltage rating of twice the maximum input voltage. additionally, some bulk capacitance can be required, especially if the lmr23615-q1 circuit is not located within approximately 5 cm from the input voltage source. this capacitor is used to provide damping to the voltage spike due to the lead inductance of the cable or the trace. for this design, two 4.7- f, 50-v, x7r ceramic capacitors are used. for high-frequency filtering place a 0.1- f capacitor as close as possible to the device pins. 8.2.2.8 bootstrap capacitor selection every lmr23615-q1 design requires a bootstrap capacitor (c boot ). the recommended capacitor is 0.1 f and rated 16 v or higher. the bootstrap capacitor is located between the sw pin and the boot pin. the bootstrap capacitor must be a high-quality ceramic type with an x7r or x5r grade dielectric for temperature stability. 8.2.2.9 vcc capacitor selection the vcc pin is the output of an internal ldo for lmr23615-q1. to insure stability of the device, place a minimum of 2.2- f, 16-v, x7r capacitor from vcc pin to ground. 8.2.2.10 undervoltage lockout setpoint the system uvlo is adjusted using the external voltage divider network of r ent and r enb . the uvlo has two thresholds, one for power up when the input voltage is rising and one for power down or brownouts when the input voltage is falling. use equation 20 to determine the v in uvlo level. (20) the en rising threshold (v enh ) for lmr23615-q1 is set to be 1.55 v (typical). choose the value of r enb to be 287 k to minimize input current from the supply. if the desired v in uvlo level is at 6 v, the value of r ent can be calculated using equation 21 : (21) equation 21 yields a value of 820 k . the resulting falling uvlo threshold, equals 4.4 v, can be calculated by equation 22 , where en hysteresis (v en_hys ) is 0.4 v (typical). (22) ff x fbt 1 c 4 f r s u u x out out 8.32 f v c u in _ rising ent enb enh v r 1 r v u ? ? ? 1 ent enb in _ falling enh en _ hys enb r r v v v r u ent enb in _ rising enh enb r r v v r u
22 lmr23615-q1 snvsas5 ? march 2018 www.ti.com product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2.3 application curves unless otherwise specified the following conditions apply: v in = 12 v, f sw = 1600 khz, l = 4.7 h, c out = 47 f, t a = 25 c. v out = 5 v i out = 1.5 a f sw = 1600 khz figure 23. ccm mode v out = 5 v i out = 0 ma f sw = 1600 khz figure 24. pfm mode v in = 12 v v out = 5 v i out = 1.5 a figure 25. start-up by v in v in = 12 v v out = 5 v i out = 1.5 a figure 26. start-up by en v in = 12 v v out = 5 v i out = 0.2 a to 1.5 a, 100 ma / s figure 27. load transient v out = 5 v i out = 1.5 a v in = 8 v to 36 v, 2 v / s figure 28. line transient
23 lmr23615-q1 www.ti.com snvsas5 ? march 2018 product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated unless otherwise specified the following conditions apply: v in = 12 v, f sw = 1600 khz, l = 4.7 h, c out = 47 f, t a = 25 c. v out = 5 v i out = 1 a to short figure 29. short protection v out = 5 v i out = short to 1 a figure 30. short recovery 9 power supply recommendations the lmr23615-q1 is designed to operate from an input voltage supply range between 4 v and 36 v. this input supply must be able to withstand the maximum input current and maintain a stable voltage. the resistance of the input supply rail must be low enough that an input current transient does not cause a high enough drop at the lmr23615-q1 supply voltage that can cause a false uvlo fault triggering and system reset. if the input supply is located more than a few inches from the lmr23615-q1, additional bulk capacitance may be required in addition to the ceramic input capacitors. the amount of bulk capacitance is not critical, but a 47- f or 100- f electrolytic capacitor is a typical choice. 10 layout 10.1 layout guidelines layout is a critical portion of good power supply design. the following guidelines will help users design a pcb with the best power conversion performance, thermal performance, and minimized generation of unwanted emi. 1. the input bypass capacitor c in must be placed as close as possible to the vin and pgnd pins. grounding for both the input and output capacitors must consist of localized top side planes that connect to the pgnd pin and pad. 2. place bypass capacitors for v cc close to the vcc pin and ground the bypass capacitor to device ground. 3. minimize trace length to the fb pin net. both feedback resistors, locate r fbt and r fbb close to the fb pin. place c ff directly in parallel with r fbt . if v out accuracy at the load is important, make sure v out sense is made at the load. route v out sense path away from noisy nodes and preferably through a layer on the other side of a shielded layer. 4. use ground plane in one of the middle layers as noise shielding and heat dissipation path. 5. have a single point ground connection to the plane. route the ground connections for the feedback and enable components to the ground plane. this prevents any switched or load currents from flowing in the analog ground traces. if not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. 6. make v in , v out and ground bus connections as wide as possible. this reduces any voltage drops on the input or output paths of the converter and maximizes efficiency. 7. provide adequate device heat sinking. use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom pcb layer. if the pcb has multiple copper layers, these thermal vias can also be connected to inner layer heat-spreading ground planes. ensure enough copper area is used for heat-sinking to keep the junction temperature below 125 c.
24 lmr23615-q1 snvsas5 ? march 2018 www.ti.com product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated layout guidelines (continued) 10.1.1 compact layout for emi reduction radiated emi is generated by the high di/dt components in pulsing currents in switching converters. the larger area covered by the path of a pulsing current, the more emi is generated. high-frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of the pulsing current. placing ceramic bypass capacitor(s) as close as possible to the vin and pgnd pins is the key to emi reduction. the sw pin connecting to the inductor must be as short as possible, and just wide enough to carry the load current without excessive heating. use short, thick traces or copper pours (shapes) for high-current conduction path to minimize parasitic resistance. place the output capacitors close to the v out end of the inductor and closely grounded to pgnd pin and exposed pad. place the bypass capacitors on vcc as close as possible to the pin and closely grounded to pgnd and the exposed pad. 10.1.2 ground plane and thermal considerations ti recommends using one of the middle layers as a solid ground plane. ground plane provides shielding for sensitive circuits and traces. it also provides a quiet reference potential for the control circuitry. connect the agnd and pgnd pins to the ground plane using vias right next to the bypass capacitors. pgnd pin is connected to the source of the internal ls switch. they should be connected directly to the grounds of the input and output capacitors. the pgnd net contains noise at switching frequency and may bounce due to load variations. pgnd trace, as well as vin and sw traces, should be constrained to one side of the ground plane. the other side of the ground plane contains much less noise and must be used for sensitive routes. ti recommends providing adequate device heat sinking by utilizing the pad of the ic as the primary thermal path. use a minimum 4 by 2 array of 12 mil thermal vias to connect the pad to the system ground plane heat sink. the vias must be evenly distributed under the pad. use as much copper as possible, for system ground plane, on the top and bottom layers for the best heat dissipation. use a four-layer board with the copper thickness for the four layers, starting from the top of, 2 oz / 1 oz / 1 oz / 2 oz. four layer boards with enough copper thickness provides low current conduction impedance, proper shielding and lower thermal resistance. the thermal characteristics of the lmr23615-q1 are specified using the parameter r ja , which characterize the junction temperature of silicon to the ambient temperature in a specific system. although the value of r ja is dependent on many variables, it still can be used to approximate the operating junction temperature of the device. to obtain an estimate of the device junction temperature, one may use equation 23 : t j = p d x r ja + t a where ? t j = junction temperature in c ? p d = v in i in (1 ? efficiency) ? 1.1 i out 2 dcr in watt ? dcr = inductor dc parasitic resistance in ? r ja = junction-to-ambient thermal resistance of the device in c/w ? t a = ambient temperature in c (23) the maximum operating junction temperature of the lmr23615-q1 is 125 c. r ja is highly related to pcb size and layout, as well as environmental factors such as heat sinking and air flow. 10.1.3 feedback resistors to reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and c ff close to the fb pin, rather than close to the load. the fb pin is the input to the error amplifier, so it is a high impedance node and very sensitive to noise. placing the resistor divider and c ff closer to the fb pin reduces the trace length of fb signal and reduces noise coupling. the output node is a low impedance node, so the trace from v out to the resistor divider can be long if short path is not available.
25 lmr23615-q1 www.ti.com snvsas5 ? march 2018 product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated layout guidelines (continued) if voltage accuracy at the load is important, make sure voltage sense is made at the load. doing so will correct for voltage drops along the traces and provide the best output accuracy. the voltage sense trace from the load to the feedback resistor divider should be routed away from the sw node path and the inductor to avoid contaminating the feedback signal with switch noise, while also minimizing the trace length. this is most important when high value resistors are used to set the output voltage. it is recommended to route the voltage sense trace and place the resistor divider on a different layer than the inductor and sw node path, such that there is a ground plane in between the feedback trace and inductor/sw node polygon. this provides further shielding for the voltage feedback path from emi noises. 10.2 layout example figure 31. lmr23615-q1 layout uvlo adjust resistor input bypass capacitor output bypass capacitor boot capacitor thermal via via (connect to gnd plane) output inductor output voltage set resistor vcc capacitor swsw boot vcc fb rt pgnd nc vin vin en/sync agnd rt
26 lmr23615-q1 snvsas5 ? march 2018 www.ti.com product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 11 device and documentation support 11.1 device support 11.1.1 development support 11.1.1.1 custom design with webench ? tools click here to create a custom design using the lmr23615-q1 device with the webench ? power designer. 1. start by entering the input voltage (v in ), output voltage (v out ), and output current (i out ) requirements. 2. optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. compare the generated design with other possible solutions from texas instruments. the webench power designer provides a customized schematic along with a list of materials with real-time pricing and component availability. in most cases, these actions are available: ? run electrical simulations to see important waveforms and circuit performance ? run thermal simulations to understand board thermal performance ? export customized schematic and layout into popular cad formats ? print pdf reports for the design, and share the design with colleagues get more information about webench tools at www.ti.com/webench . 11.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks powerpad, e2e are trademarks of texas instruments. webench, simple switcher are registered trademarks of texas instruments. all other trademarks are the property of their respective owners. 11.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions.
27 lmr23615-q1 www.ti.com snvsas5 ? march 2018 product folder links: lmr23615-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 12-mar-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples LMR23615QDRRRQ1 active son drr 12 3000 green (rohs & no sb/br) cu sn level-2-260c-1 year -40 to 125 3615q lmr23615qdrrtq1 active son drr 12 250 green (rohs & no sb/br) cu sn level-2-260c-1 year -40 to 125 3615q (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 12-mar-2018 addendum-page 2 other qualified versions of lmr23615-q1 : ? catalog: lmr23615 note: qualified version definitions: ? catalog - ti's standard catalog product
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant LMR23615QDRRRQ1 son drr 12 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 q2 lmr23615qdrrtq1 son drr 12 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 q2 package materials information www.ti.com 11-mar-2018 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) LMR23615QDRRRQ1 son drr 12 3000 370.0 355.0 55.0 lmr23615qdrrtq1 son drr 12 250 195.0 200.0 45.0 package materials information www.ti.com 11-mar-2018 pack materials-page 2

a a www.ti.com package outline c 12x 0.3 0.2 2.5 0.1 2x 2.5 1.7 0.1 10x 0.5 0.8 max 12x 0.38 0.28 0.05 0.00 a 3.1 2.9 b 3.1 2.9 (0.2) typ 0.1 min (0.05) wson - 0.8 mm max height drr0012d plastic small outline - no lead 4223146/c 02/2018 pin 1 index area seating plane 0.08 c 1 6 7 12 (optional) pin 1 id 0.1 c a b 0.05 c thermal pad exposed 13 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. the package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. scale 4.000 scale 30.000 section a-a section a-a typical
www.ti.com example board layout 0.07 min all around 0.07 max all around 12x (0.25) (2.5) (2.87) 10x (0.5) (1.7) ( 0.2) via typ (0.6) (1) 12x (0.53) (r0.05) typ wson - 0.8 mm max height drr0012d plastic small outline - no lead 4223146/c 02/2018 symm 1 6 7 12 land pattern example exposed metal shown scale:20x 13 notes: (continued) 4. this package is designed to be soldered to a thermal pad on the board. for more information, see texas instruments literature number slua271 (www.ti.com/lit/slua271). 5. vias are optional depending on application, refer to device data sheet. if any vias are implemented, refer to their locations shown on this view. it is recommended that vias under paste be filled, plugged or tented. symm solder mask opening solder mask metal under solder mask defined exposed metal metal edge solder mask opening solder mask details non solder mask defined (preferred) exposed metal
www.ti.com example stencil design (r0.05) typ 12x (0.25) 12x (0.53) (0.74) (1.15) (2.87) (0.675) 10x (0.5) (0.47) wson - 0.8 mm max height drr0012d plastic small outline - no lead 4223146/c 02/2018 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. solder paste example based on 0.125 mm thick stencil exposed pad 80.1% printed solder coverage by area scale:25x symm 1 6 7 12 metal typ symm 13
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